<feed xmlns='http://www.w3.org/2005/Atom'>
<title>BMC/Intel-BMC/linux.git/arch/arm/include/asm/mach/arch.h, branch dev</title>
<subtitle>Intel OpenBMC Linux kernel source tree (mirror)</subtitle>
<id>https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev</id>
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<updated>2015-06-01T22:45:56+00:00</updated>
<entry>
<title>ARM: keystone2: rename init_meminfo to pv_fixup</title>
<updated>2015-06-01T22:45:56+00:00</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2015-04-04T09:01:10+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=c0b759d87eab301af0380f5459057656178e78cf'/>
<id>urn:sha1:c0b759d87eab301af0380f5459057656178e78cf</id>
<content type='text'>
The init_meminfo() method is not about initialising meminfo - it's about
fixing up the physical to virtual translation so that we use a different
physical address space, possibly above the 4GB physical address space.
Therefore, the name "init_meminfo()" is confusing.

Rename it to pv_fixup() instead.

Acked-by: Santosh Shilimkar &lt;ssantosh@kernel.org&gt;
Tested-by: Murali Karicheri &lt;m-karicheri2@ti.com&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
</entry>
<entry>
<title>ARM: keystone2: move update of the phys-to-virt constants into generic code</title>
<updated>2015-06-01T22:45:50+00:00</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2015-04-04T08:53:38+00:00</published>
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<id>urn:sha1:c8ca2b4b29282605698968d15667939b23e208e2</id>
<content type='text'>
Make the init_meminfo function return the offset to be applied to the
phys-to-virt translation constants.  This allows us to move the update
into generic code, along with the requirements for this update.

This avoids platforms having to know the details of the phys-to-virt
translation support.

Acked-by: Santosh Shilimkar &lt;ssantosh@kernel.org&gt;
Tested-by: Murali Karicheri &lt;m-karicheri2@ti.com&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
</entry>
<entry>
<title>arm: Add devicetree fixup machine function</title>
<updated>2014-07-30T03:26:49+00:00</updated>
<author>
<name>Laura Abbott</name>
<email>lauraa@codeaurora.org</email>
</author>
<published>2014-07-15T17:03:36+00:00</published>
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<id>urn:sha1:5a12a597a8627b91fd9d94365853f9f69a4f399c</id>
<content type='text'>
Commit 1c2f87c22566cd057bc8cde10c37ae9da1a1bb76
(ARM: 8025/1: Get rid of meminfo) dropped the upper bound on
the number of memory banks that can be added as there was no
technical need in the kernel. It turns out though, some bootloaders
(specifically the arndale-octa exynos boards) may pass invalid memory
information and rely on the kernel to not parse this data. This is a
bug in the bootloader but we still need to work around this.
Work around this by introducing a dt_fixup function. This function
gets called before the flattened devicetree is scanned for memory
and the like. In this fixup function for exynos, limit the maximum
number of memory regions in the devicetree.

Signed-off-by: Laura Abbott &lt;lauraa@codeaurora.org&gt;
Tested-by: Andreas Färber &lt;afaerber@suse.de&gt;
[glikely: Added a comment and fixed up function name]
Signed-off-by: Grant Likely &lt;grant.likely@linaro.org&gt;
</content>
</entry>
<entry>
<title>Merge branches 'alignment', 'fixes', 'l2c' (early part) and 'misc' into for-next</title>
<updated>2014-06-05T11:35:52+00:00</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2014-06-05T11:35:52+00:00</published>
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<id>urn:sha1:1fb333489fb917c704ad43e51b45c12f52215a9c</id>
<content type='text'>
</content>
</entry>
<entry>
<title>ARM: 8025/1: Get rid of meminfo</title>
<updated>2014-06-01T00:17:12+00:00</updated>
<author>
<name>Laura Abbott</name>
<email>lauraa@codeaurora.org</email>
</author>
<published>2014-04-13T21:54:58+00:00</published>
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<id>urn:sha1:1c2f87c22566cd057bc8cde10c37ae9da1a1bb76</id>
<content type='text'>
memblock is now fully integrated into the kernel and is the prefered
method for tracking memory. Rather than reinvent the wheel with
meminfo, migrate to using memblock directly instead of meminfo as
an intermediate.

Acked-by: Jason Cooper &lt;jason@lakedaemon.net&gt;
Acked-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
Acked-by: Santosh Shilimkar &lt;santosh.shilimkar@ti.com&gt;
Acked-by: Kukjin Kim &lt;kgene.kim@samsung.com&gt;
Tested-by: Marek Szyprowski &lt;m.szyprowski@samsung.com&gt;
Tested-by: Leif Lindholm &lt;leif.lindholm@linaro.org&gt;
Signed-off-by: Laura Abbott &lt;lauraa@codeaurora.org&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
</entry>
<entry>
<title>ARM: l2c: add platform independent core L2 cache OF initialisation</title>
<updated>2014-05-29T23:49:00+00:00</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2014-04-28T14:24:10+00:00</published>
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<id>urn:sha1:805604ef8596968e5f251c69fd92bd3b8f466317</id>
<content type='text'>
Add a hook into the core ARM code to perform L2 cache initialisation
in a platform independent manner.  Platforms still get to indicate
their auxiliary control register values and mask, but the
initialisation call will now be made from generic code.

Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
</entry>
<entry>
<title>ARM: mm: Recreate kernel mappings in early_paging_init()</title>
<updated>2013-10-11T00:28:19+00:00</updated>
<author>
<name>Santosh Shilimkar</name>
<email>santosh.shilimkar@ti.com</email>
</author>
<published>2013-07-31T16:44:46+00:00</published>
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<id>urn:sha1:a77e0c7b2774fd52ce6bf25c2c3ffdccb7b110ff</id>
<content type='text'>
This patch adds a step in the init sequence, in order to recreate
the kernel code/data page table mappings prior to full paging
initialization.  This is necessary on LPAE systems that run out of
a physical address space outside the 4G limit.  On these systems,
this implementation provides a machine descriptor hook that allows
the PHYS_OFFSET to be overridden in a machine specific fashion.

Cc: Russell King &lt;linux@arm.linux.org.uk&gt;

Acked-by: Nicolas Pitre &lt;nico@linaro.org&gt;
Signed-off-by: R Sricharan &lt;r.sricharan@ti.com&gt;
Signed-off-by: Santosh Shilimkar &lt;santosh.shilimkar@ti.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'late-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc</title>
<updated>2013-09-09T23:35:29+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2013-09-09T23:35:29+00:00</published>
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<id>urn:sha1:640414171818c6293c23e74a28d1c69b2a1a7fe5</id>
<content type='text'>
Pull ARM SoC late changes from Kevin Hilman:
 "These are changes that arrived a little late before the merge window,
  or had dependencies on previous branches.

  Highlights:
   - ux500: misc.  cleanup, fixup I2C devices
   - exynos: DT updates for RTC; PM updates
   - at91: DT updates for NAND; new platforms added to generic defconfig
   - sunxi: DT updates: cubieboard2, pinctrl driver, gated clocks
   - highbank: LPAE fixes, select necessary ARM errata
   - omap: PM fixes and improvements; OMAP5 mailbox support
   - omap: basic support for new DRA7xx SoCs"

* tag 'late-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (60 commits)
  ARM: dts: vexpress: Add CCI node to TC2 device-tree
  ARM: EXYNOS: Skip C1 cpuidle state for exynos5440
  ARM: EXYNOS: always enable PM domains support for EXYNOS4X12
  ARM: highbank: clean-up some unused includes
  ARM: sun7i: Enable the A20 clocks in the DTSI
  ARM: sun6i: Enable clock support in the DTSI
  ARM: sun5i: dt: Use the A10s gates in the DTSI
  ARM: at91: at91_dt_defconfig: enable rm9200 support
  ARM: dts: add ADC device tree node for exynos5420/5250
  ARM: dts: Add RTC DT node to Exynos5420 SoC
  ARM: dts: Update the "status" property of RTC DT node for Exynos5250 SoC
  ARM: dts: Fix the RTC DT node name for Exynos5250
  irqchip: mmp: avoid to include irqs head file
  ARM: mmp: avoid to include head file in mach-mmp
  irqchip: mmp: support irqchip
  irqchip: move mmp irq driver
  ARM: OMAP: AM33xx: clock: Add RNG clock data
  ARM: OMAP: TI81XX: add always-on powerdomain for TI81XX
  ARM: OMAP4: clock: Lock PLLs in the right sequence
  ARM: OMAP: AM33XX: hwmod: Add hwmod data for debugSS
  ...
</content>
</entry>
<entry>
<title>ARM: use phys_addr_t for DMA zone sizes</title>
<updated>2013-08-13T20:52:33+00:00</updated>
<author>
<name>Rob Herring</name>
<email>rob.herring@calxeda.com</email>
</author>
<published>2013-08-01T20:29:29+00:00</published>
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<id>urn:sha1:364230b9952143eb2062dc071e919fb751540ae8</id>
<content type='text'>
In order to specify a DMA zone size of 4GB on LPAE systems, the sizes need
to be 64-bit. So make machine_desc.dma_zone_size and arm_dma_zone_size be
phys_addr_t instead of unsigned long.

Signed-off-by: Rob Herring &lt;rob.herring@calxeda.com&gt;
</content>
</entry>
<entry>
<title>ARM: constify machine_desc structure uses</title>
<updated>2013-07-26T13:55:59+00:00</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2013-07-26T13:55:59+00:00</published>
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<id>urn:sha1:ff69a4c855066592f9e293cff8f54813614dd544</id>
<content type='text'>
struct machine_desc records are defined everywhere as a 'const'
structure, but unfortuantely it loses its const-ness through the use of
linker magic - the symbols which surround the section are not declared
const so it becomes possible not to use 'const' for pointers to these
const structures.

Let's fix this oversight - all pointers to these structures should be
marked const too.

Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
</entry>
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