Intel OpenBMC Linux kernel source tree (mirror) https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev 2015-06-23T21:08:54+00:00 2015-06-23T21:08:54+00:00 Linus Torvalds torvalds@linux-foundation.org 2015-06-23T21:08:54+00:00 urn:sha1:cb8a4deaf9b2778653c4391d8ccb24c5ab159f9d Pull trivial tree updates from Jiri Kosina: "As usual, mostly comment, kerneldoc and printk() fixes" * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial: lpfc: Grammar s/an negative/a negative/ ARM: lib/lib1funcs.S: fix typo s/substractions/subtractions/ cx25821: cx25821-medusa-reg.h: fix 0x0x prefix lib: crc-itu-t.[ch] fix 0x0x prefix in integer constants rapidio: Fix kerneldoc and comment qla4xxx: Fix printk() in qla4_83xx_read_reset_template() and qla4_83xx_pre_loopback_config() treewide: Kconfig: fix wording / spelling usb/serial: fix grammar in Kconfig help text for FTDI_SIO megaraid_sas: fix kerneldoc netfilter: ebtables: fix comment grammar drm/radeon: fix comment isdn: fix grammar in comment ARM: KVM: fix comment 2015-05-26T13:07:07+00:00 Geert Uytterhoeven geert+renesas@glider.be 2015-03-03T10:58:06+00:00 urn:sha1:47b2d14294e04918205950f824fe099505cd4a03 Fix spelling in comment. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Jiri Kosina <jkosina@suse.cz> 2015-01-16T13:40:14+00:00 Mario Smarduch m.smarduch@samsung.com 2015-01-15T23:58:55+00:00 urn:sha1:72fc36b600f73e37557576af80c58836dcf389f9 This patch adds ARMv7 architecture TLB Flush function. Acked-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Mario Smarduch <m.smarduch@samsung.com> 2014-07-11T11:57:38+00:00 Victor Kamensky victor.kamensky@linaro.org 2014-06-12T16:30:02+00:00 urn:sha1:19b0e60a63f758a28329aa40f4270a6c98c2dcb7 In some cases the mcrr and mrrc instructions in combination with the ldrd and strd instructions need to deal with 64bit value in memory. The ldrd and strd instructions already handle endianness within word (register) boundaries but to get effect of the whole 64bit value represented correctly, rr_lo_hi macro is introduced and is used to swap registers positions when the mcrr and mrrc instructions are used. That has the effect of swapping two words. Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> 2014-03-03T01:15:24+00:00 Marc Zyngier marc.zyngier@arm.com 2014-01-22T10:20:09+00:00 urn:sha1:af20814ee927ed888288d98917a766b4179c4fe0 HCR.TVM traps (among other things) accesses to AMAIR0 and AMAIR1. In order to minimise the amount of surprise a guest could generate by trying to access these registers with caches off, add them to the list of registers we switch/handle. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com> 2013-10-13T00:45:30+00:00 Jonathan Austin jonathan.austin@arm.com 2013-09-26T15:49:28+00:00 urn:sha1:e8c2d99f8277d68d28a9f99d16289712bc2aee7f This patch adds support for running Cortex-A7 guests on Cortex-A7 hosts. As Cortex-A7 is architecturally compatible with A15, this patch is largely just generalising existing code. Areas where 'implementation defined' behaviour is identical for A7 and A15 is moved to allow it to be used by both cores. The check to ensure that coprocessor register tables are sorted correctly is also moved in to 'common' code to avoid each new cpu doing its own check (and possibly forgetting to do so!) Signed-off-by: Jonathan Austin <jonathan.austin@arm.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> 2013-06-26T17:50:04+00:00 Marc Zyngier marc.zyngier@arm.com 2013-06-21T12:08:46+00:00 urn:sha1:6a077e4ab9cbfbf279fb955bae05b03781c97013 Not saving PAR is an unfortunate oversight. If the guest performs an AT* operation and gets scheduled out before reading the result of the translation from PAR, it could become corrupted by another guest or the host. Saving this register is made slightly more complicated as KVM also uses it on the permission fault handling path, leading to an ugly "stash and restore" sequence. Fortunately, this is already a slow path so we don't really care. Also, Linux doesn't do any AT* operation, so Linux guests are not impacted by this bug. [ Slightly tweaked to use an even register as first operand to ldrd and strd operations in interrupts_head.S - Christoffer ] Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> 2013-06-26T17:50:02+00:00 Marc Zyngier marc.zyngier@arm.com 2013-05-14T11:11:35+00:00 urn:sha1:368074d908b785588778f00b4384376cd636f4a1 __kvm_tlb_flush_vmid has been renamed to __kvm_tlb_flush_vmid_ipa, and the old prototype should have been removed when the code was modified. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <cdall@cs.columbia.edu> 2013-03-06T23:48:45+00:00 Marc Zyngier marc.zyngier@arm.com 2013-01-28T15:27:00+00:00 urn:sha1:48762767e1c150d58c250650f8202b7d4ad65ec4 v8 is capable of invalidating Stage-2 by IPA, but v7 is not. Change kvm_tlb_flush_vmid() to take an IPA parameter, which is then ignored by the invalidation code (and nuke the whole TLB as it always did). This allows v8 to implement a more optimized strategy. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> 2013-02-11T19:05:38+00:00 Marc Zyngier marc.zyngier@arm.com 2013-01-23T18:21:59+00:00 urn:sha1:c7e3ba64ba16eddfbfc66ec099860f40e808e124 Do the necessary save/restore dance for the timers in the world switch code. In the process, allow the guest to read the physical counter, which is useful for its own clock_event_device. Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>