BMC/Intel-BMC/linux.git/arch/arc/mm/tlb.c, branch dev

ARCv2: MMUv4: TLB programming Model changes

2015-06-22T08:36:55+00:00

Signed-off-by: Vineet Gupta

ARC: compress cpuinfo_arc_mmu (mainly save page size in KB)

2015-06-19T12:39:25+00:00

Signed-off-by: Vineet Gupta

ARC: boot: cpu feature print enhancements

2014-10-13T09:16:22+00:00

Signed-off-by: Vineet Gupta

ARC: [SMP] TLB flush

2013-11-06T05:11:45+00:00

- Add mm_cpumask setting (aggregating only, unlike some other arches) used to restrict the TLB flush cross-calling - cross-calling versions of TLB flush routines (thanks to Noam) Signed-off-by: Noam Camus Signed-off-by: Vineet Gupta

ARC: [SMP] ASID allocation

2013-11-06T05:11:45+00:00

-Track a Per CPU ASID counter -mm-per-cpu ASID (multiple threads, or mm migrated around) Signed-off-by: Vineet Gupta

ARC: Fix bogus gcc warning and micro-optimise TLB iteration loop

2013-11-06T05:11:41+00:00

------------------>8---------------------- arch/arc/mm/tlb.c: In function ‘do_tlb_overlap_fault’: arch/arc/mm/tlb.c:688:13: warning: array subscript is above array bounds [-Warray-bounds] (pd0[n] & PAGE_MASK)) { ^ ------------------>8---------------------- While at it, remove the usless last iteration of outer loop when reading a TLB SET for duplicate entries. Suggested-by: Mischa Jonker Signed-off-by: Vineet Gupta

ARC: [ASID] Track ASID allocation cycles/generations

2013-08-30T16:12:19+00:00

This helps remove asid-to-mm reverse map While mm->context.id contains the ASID assigned to a process, our ASID allocator also used asid_mm_map[] reverse map. In a new allocation cycle (mm->ASID >= @asid_cache), the Round Robin ASID allocator used this to check if new @asid_cache belonged to some mm2 (from prev cycle). If so, it could locate that mm using the ASID reverse map, and mark that mm as unallocated ASID, to force it to refresh at the time of switch_mm() However, for SMP, the reverse map has to be maintained per CPU, so becomes 2 dimensional, hence got rid of it. With reverse map gone, it is NOT possible to reach out to current assignee. So we track the ASID allocation generation/cycle and on every switch_mm(), check if the current generation of CPU ASID is same as mm's ASID; If not it is refreshed. (Based loosely on arch/sh implementation) Signed-off-by: Vineet Gupta

ARC: [ASID] get_new_mmu_context() to conditionally allocate new ASID

2013-08-30T16:12:18+00:00

ASID allocation changes/1 This patch does 2 things: (1) get_new_mmu_context() NOW moves mm->ASID to a new value ONLY if it was from a prev allocation cycle/generation OR if mm had no ASID allocated (vs. before would unconditionally moving to a new ASID) Callers desiring unconditional update of ASID, e.g.local_flush_tlb_mm() (for parent's address space invalidation at fork) need to first force the parent to an unallocated ASID. (2) get_new_mmu_context() always sets the MMU PID reg with unchanged/new ASID value. The gains are: - consolidation of all asid alloc logic into get_new_mmu_context() - avoiding code duplication in switch_mm() for PID reg setting - Enables future change to fold activate_mm() into switch_mm() Signed-off-by: Vineet Gupta

ARC: [ASID] Refactor the TLB paranoid debug code

2013-08-30T16:12:18+00:00

-Asm code already has values of SW and HW ASID values, so they can be passed to the printing routine. Signed-off-by: Vineet Gupta

ARC: No need to flush the TLB in early boot

2013-08-30T05:18:14+00:00

Signed-off-by: Vineet Gupta