BMC/Intel-BMC/linux.git/arch/arc/include/asm/arcregs.h, branch devIntel OpenBMC Linux kernel source tree (mirror)https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev2015-08-03T14:04:07+00:00ARCv2: Fix the peripheral address space detection2015-08-03T14:04:07+00:00Vineet Guptavgupta@synopsys.com2015-08-03T10:07:24+00:00urn:sha1:e13c42ecbe580509451e021ba2586871e5b47640
With HS 2.1 release, the peripheral space register no longer contains
the uncached space specifics, causing the kernel to panic early on.
So read the newer NON VOLATILE AUX register to get that info.
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
ARCv2: MMUv4: cache programming model changes2015-06-22T08:36:55+00:00Vineet Guptavgupta@synopsys.com2015-04-06T11:53:57+00:00urn:sha1:d1f317d8254413447bcd6b6adbde24a985d256c2
Caveats about cache flush on ARCv2 based cores
- dcache is PIPT so paddr is sufficient for cache maintenance ops (no
need to setup PTAG reg
- icache is still VIPT but only aliasing configs need PTAG setup
So basically this is departure from MMU-v3 which always need vaddr in
line ops registers (DC_IVDL, DC_FLDL, IC_IVIL) but paddr in DC_PTAG,
IC_PTAG respectively.
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
ARCv2: MMUv4: TLB programming Model changes2015-06-22T08:36:55+00:00Vineet Guptavgupta@synopsys.com2015-04-06T11:52:39+00:00urn:sha1:d7a512bfe0be3790bae8465b4cb6c1bbca03c616
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
ARCv2: Support for ARCv2 ISA and HS38x cores2015-06-22T08:36:55+00:00Vineet Guptavgupta@synopsys.com2013-05-13T13:00:41+00:00urn:sha1:1f6ccfff6314672743ad7252160654709e997a2a
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
ARCv2: [intc] HS38 core interrupt controller2015-06-22T08:36:55+00:00Vineet Guptavgupta@synopsys.com2015-03-06T08:38:20+00:00urn:sha1:820970a5aa3c98be26e1df64da4b93294d20d4e7
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
ARC: uncached base is hard constant for ARC, don't save it2015-06-22T08:36:54+00:00Vineet Guptavgupta@synopsys.com2015-04-16T14:19:12+00:00urn:sha1:10d11e580c50f8a6718a58f92198dbc031e63b0a
ioremap already uses the hard define, just make sure BCR value matches
that
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
ARC: entry.S: Introduce INTERRUPT_{PROLOGUE,EPILOGUE}2015-06-19T12:39:34+00:00Vineet Guptavgupta@synopsys.com2014-10-13T12:43:35+00:00urn:sha1:09f3b37e4e3bbe22444617c273a3c046aade5db2
-common'ize macros for level 1 and level 2 interrupts
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
ARC: compress cpuinfo_arc_mmu (mainly save page size in KB)2015-06-19T12:39:25+00:00Vineet Guptavgupta@synopsys.com2015-02-13T13:03:47+00:00urn:sha1:40b552d95a545e828fb4ebbf68a385cb9eaebf64
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
ARC: Fix RTT boot printing2015-04-13T09:45:17+00:00Vineet Guptavgupta@synopsys.com2015-03-08T08:48:21+00:00urn:sha1:a44ec8bd2a55c7644d458d8e79d83bd9204e1796
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
ARC: cosmetic: Remove unused ECR bitfield masks2015-04-13T09:44:57+00:00Vineet Guptavgupta@synopsys.com2014-09-22T12:24:45+00:00urn:sha1:dc9e234f91c77a98a8911bf02619275f51b14bfc
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>