BMC/Intel-BMC/linux.git/Documentation, branch dev-5.14-intel

mailbox: ioctl to fetch mailbox size

2021-10-19T22:10:38+00:00

The size of mailbox differ from AST2500, AST2600 A0 and A1. Add an ioctl support to fetch the mailbox size. Tested: Verfied ioctl call returns mailbox size as expected. Change-Id: I4e261aaf8aa3fb108d6ad152d30a17b114d70ccd Signed-off-by: Arun P. Mohanan

Add AST2500 eSPI driver

2021-10-19T22:10:36+00:00

When PCH works under eSPI mode, the PMC (Power Management Controller) in PCH is waiting for SUS_ACK from BMC after it alerts SUS_WARN. It is in dead loop if no SUS_ACK assert. This is the basic requirement for the BMC works as eSPI slave. Also for the host power on / off actions, from BMC side, the following VW (Virtual Wire) messages are done in firmware: 1. SLAVE_BOOT_LOAD_DONE / SLAVE_BOOT_LOAD_STATUS 2. SUS_ACK 3. OOB_RESET_ACK 4. HOST_RESET_ACK Also, it provides monitoring interface of PLTRST_N signal through /dev/espi-pltrstn Signed-off-by: Haiyue Wang Signed-off-by: Jae Hyun Yoo Signed-off-by: James Feist Signed-off-by: Vernon Mauery

hwmon: peci: add energy sensor to peci-cpupower

2021-10-19T22:10:35+00:00

Add support for energy consumption of CPU package sensor. Energy is reported in micro Joules and exposed under energyN_input file. Signed-off-by: Olender, Agata

hwmon: peci: dimmpower implementation

2021-10-19T22:10:34+00:00

1. Peci dimmpower module implementation. 2. Enable DIMM avarage power, power limit, power limit max setting, power limit min setting reading and expose them under power1_avarage, power1_cap, power1_cap_max, power1_cap_min in sysfs. 3. Enable DIMM power limit writing through power1_cap. Tested: * on WilsonCity platform, * power1_avarage, power1_cap, power1_cap_max and power1_cap_min work as expected Signed-off-by: Zbigniew Lukwinski

hwmon: peci: cpupower extension

2021-10-19T22:10:34+00:00

1. Use hwmon peci pcs utils to refactor peci cpupower module. 2. Enable CPU power limit, power limit max (TDP) setting, power limit min setting reading and expose them under power1_cap, power1_cap_max, power1_cap_min. 3. Enable CPU power limit writing through power1_cap. Tested: * on WilsonCity platform, * power1_avarage works as before the change, * power1_cap, power1_cap_max, power1_cap_min work as expected. Signed-off-by: Zbigniew Lukwinski

arm: dts: aspeed-g6: Add ast2600-mctp node

2021-10-19T22:10:33+00:00

AST2600 provides MCTP over PCIe controller allowing BMC to communicate with devices on host PCIe bus. We are also adding syscon node describing PCIe Host controller device which can be used to gather information on PCIe enumeration (and assigned address). Signed-off-by: Iwona Winiarska

i2c: aspeed: add general call support

2021-10-19T22:10:32+00:00

This commit adds general call support into Aspeed I2C driver. This is downstream only customization so it should not go into upstream. Signed-off-by: Jae Hyun Yoo

i2c: aspeed: add DMA mode transfer support

2021-10-19T22:10:32+00:00

This commit adds DMA mode transfer support. Only AST2500 supports DMA mode under some limitations: I2C is sharing the DMA H/W with UHCI host controller and MCTP controller. Since those controllers operate with DMA mode only, I2C has to use buffer mode or byte mode instead if one of those controllers is enabled. Also make sure that if SD/eMMC or Port80 snoop uses DMA mode instead of PIO or FIFO respectively, I2C can't use DMA mode. Signed-off-by: Jae Hyun Yoo

Documentation jtag: Add JTAG core driver ioctl number

2021-10-19T22:10:31+00:00

JTAG class driver provide infrastructure to support hardware/software JTAG platform drivers. It provide user layer API interface for flashing and debugging external devices which equipped with JTAG interface using standard transactions. Driver exposes set of IOCTL to user space for: - XFER: SIR (Scan Instruction Register, IEEE 1149.1 Data Register scan); SDR (Scan Data Register, IEEE 1149.1 Instruction Register scan); - GIOCSTATUS read the current TAPC state of the JTAG controller - SIOCSTATE Forces the JTAG TAPC to go into a particular state. - SIOCFREQ/GIOCFREQ for setting and reading JTAG frequency. - IOCBITBANG for low level control of JTAG signals. Signed-off-by: Oleksandr Shamray Signed-off-by: Ernesto Corona Acked-by: Philippe Ombredanne Cc: Jonathan Corbet Cc: Greg Kroah-Hartman Cc: Gustavo Pimentel Cc: Lorenzo Pieralisi Cc: Kishon Vijay Abraham I Cc: Darrick J. Wong Cc: Bryant G. Ly Cc: Eric Sandeen Cc: Randy Dunlap Cc: Tomohiro Kusumi Cc: Arnd Bergmann Cc: Mauro Carvalho Chehab Cc: Alexandre Belloni Cc: "Theodore Ts'o" Cc: Eric Biggers Cc: Steven Filary Cc: Jiri Pirko Cc: Vadim Pasternak Cc: Amithash Prasad Cc: Patrick Williams Cc: Rgrs v29->v30 v28->v29 Move ioctl number to userspace-api/ioctl/ioctl-number.rst

Documentation: jtag: Add ABI documentation

2021-10-19T22:10:31+00:00

Added document that describe the ABI for JTAG class driver Signed-off-by: Oleksandr Shamray Signed-off-by: Ernesto Corona Acked-by: Arnd Bergmann Cc: Jonathan Corbet Cc: Arnd Bergmann Cc: Mauro Carvalho Chehab Cc: Linus Walleij Cc: Manivannan Sadhasivam Cc: Jeffrey Hugo Cc: Steven Filary Cc: Jiri Pirko Cc: Vadim Pasternak Cc: Amithash Prasad Cc: Patrick Williams Cc: Rgrs