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<title>BMC/Intel-BMC/linux.git/Documentation/xtensa/atomctl.txt, branch master</title>
<subtitle>Intel OpenBMC Linux kernel source tree (mirror)</subtitle>
<id>https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=master</id>
<link rel='self' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=master'/>
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<updated>2014-01-14T20:21:23+00:00</updated>
<entry>
<title>xtensa: fix ATOMCTL register documentation</title>
<updated>2014-01-14T20:21:23+00:00</updated>
<author>
<name>Baruch Siach</name>
<email>baruch@tkos.co.il</email>
</author>
<published>2013-11-11T15:15:17+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=5f42146e7599e120ee3f5b07d03ea45c633a955a'/>
<id>urn:sha1:5f42146e7599e120ee3f5b07d03ea45c633a955a</id>
<content type='text'>
Make the WT entry match table 4-52 of the Xtensa ISA RM (RD-2012.5).

Signed-off-by: Baruch Siach &lt;baruch@tkos.co.il&gt;
Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</content>
</entry>
<entry>
<title>xtensa: initialize atomctl SR</title>
<updated>2012-12-19T05:10:22+00:00</updated>
<author>
<name>Max Filippov</name>
<email>jcmvbkbc@gmail.com</email>
</author>
<published>2012-11-19T03:00:41+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=c622b29d1f38021411965b7e0170ab055551b257'/>
<id>urn:sha1:c622b29d1f38021411965b7e0170ab055551b257</id>
<content type='text'>
In order to use S32C1I instruction on cores with ATOMCTL SR the register
must be properly initialized.

Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
Signed-off-by: Chris Zankel &lt;chris@zankel.net&gt;
</content>
</entry>
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