<feed xmlns='http://www.w3.org/2005/Atom'>
<title>BMC/Intel-BMC/linux.git/Documentation/devicetree/bindings/spi, branch dev-5.2</title>
<subtitle>Intel OpenBMC Linux kernel source tree (mirror)</subtitle>
<id>https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev-5.2</id>
<link rel='self' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev-5.2'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/'/>
<updated>2019-05-02T01:37:54+00:00</updated>
<entry>
<title>dt-bindings: spi: spi-mt65xx: add support for MT8516</title>
<updated>2019-05-02T01:37:54+00:00</updated>
<author>
<name>Leilk Liu</name>
<email>leilk.liu@mediatek.com</email>
</author>
<published>2019-04-17T08:47:16+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=bf6e839657598b77e40eb18225f8660c4778cb19'/>
<id>urn:sha1:bf6e839657598b77e40eb18225f8660c4778cb19</id>
<content type='text'>
Add binding documentation of spi-mt65xx for MT8516 SOC.

Signed-off-by: Leilk Liu &lt;leilk.liu@mediatek.com&gt;
Reviewed-by: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
</content>
</entry>
<entry>
<title>spi: sh-msiof: Document r8a77470 bindings</title>
<updated>2019-05-02T01:37:48+00:00</updated>
<author>
<name>Cao Van Dong</name>
<email>cv-dong@jinso.co.jp</email>
</author>
<published>2019-04-11T07:54:21+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=9231b4603ef266cdf242d44c3164d6ee69447a1b'/>
<id>urn:sha1:9231b4603ef266cdf242d44c3164d6ee69447a1b</id>
<content type='text'>
Document SoC specific bindings for R-Car RZ/G1C(r8a77470) SoC.

Signed-off-by: Cao Van Dong &lt;cv-dong@jinso.co.jp&gt;
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
</content>
</entry>
<entry>
<title>spi: document tx/rx clock delay properties</title>
<updated>2019-04-08T07:21:45+00:00</updated>
<author>
<name>Sowjanya Komatineni</name>
<email>skomatineni@nvidia.com</email>
</author>
<published>2019-04-05T00:14:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=7558f978f9b66a2bc284a0e8c0764b88305bc29f'/>
<id>urn:sha1:7558f978f9b66a2bc284a0e8c0764b88305bc29f</id>
<content type='text'>
Tegra SPI controller has TX and RX trimmers to tuning the delay of
SPI master clock with respect to the data.

TX and RX tap values are based on the platform validation across the
PVT and the trimmer values vary based on the trace lengths to the
corresponding SPI devices.

Signed-off-by: Sowjanya Komatineni &lt;skomatineni@nvidia.com&gt;
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: spi: Add device tree binding documentation for Zynq QSPI controller</title>
<updated>2019-04-05T03:24:35+00:00</updated>
<author>
<name>Naga Sureshkumar Relli</name>
<email>naga.sureshkumar.relli@xilinx.com</email>
</author>
<published>2019-04-01T07:58:32+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=d2920ef5d094b59254bedfccb1fab984d101c332'/>
<id>urn:sha1:d2920ef5d094b59254bedfccb1fab984d101c332</id>
<content type='text'>
This patch adds the dts binding document for Zynq SOC QSPI controller.

Reviewed-by: Rob Herring &lt;robh@kernel.org&gt;
Signed-off-by: Naga Sureshkumar Relli &lt;naga.sureshkumar.relli@xilinx.com&gt;
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
</content>
</entry>
<entry>
<title>spi: mt7621: Move SPI driver out of staging</title>
<updated>2019-03-25T12:13:34+00:00</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2019-03-25T08:29:25+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=cbd66c626e16743b05af807ad48012c0a097b9fb'/>
<id>urn:sha1:cbd66c626e16743b05af807ad48012c0a097b9fb</id>
<content type='text'>
This patch moves the MT7621 SPI driver, which is used on some Ralink /
MediaTek MT76xx MIPS SoC's, out of the staging directory. No changes to
the source code are done in this patch.

This driver version was tested successfully on an MT7688 based platform
with an SPI NOR on CS0 and an SPI NAND on CS1 without any issues (so
far).

This patch also documents the devicetree bindings for the MT7621 SPI
device driver.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Cc: Rob Herring &lt;robh@kernel.org&gt;
Cc: Mark Brown &lt;broonie@kernel.org&gt;
Cc: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
Cc: NeilBrown &lt;neil@brown.name&gt;
Cc: Sankalp Negi &lt;sankalpnegi2310@gmail.com&gt;
Cc: Chuanhong Guo &lt;gch981213@gmail.com&gt;
Cc: John Crispin &lt;john@phrozen.org&gt;
Cc: Armando Miraglia &lt;arma2ff0@gmail.com&gt;
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: snps,dw-apb-ssi: Add optional clock bindings documentation</title>
<updated>2019-03-20T17:20:52+00:00</updated>
<author>
<name>Gareth Williams</name>
<email>gareth.williams.jx@renesas.com</email>
</author>
<published>2019-03-19T15:52:06+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=2f324ac7cf8c50aa079cf30445b99a1b98ea2728'/>
<id>urn:sha1:2f324ac7cf8c50aa079cf30445b99a1b98ea2728</id>
<content type='text'>
Add documentation to the Synopsys SPI dt-bindings to support an
optional interface clock that may be used for register access.

Signed-off-by: Phil Edworthy &lt;phil.edworthy@renesas.com&gt;
Signed-off-by: Gareth Williams &lt;gareth.williams.jx@renesas.com&gt;
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: snps,dw-apb-ssi: Add mandatory clock bindings documentation</title>
<updated>2019-03-20T17:20:43+00:00</updated>
<author>
<name>Phil Edworthy</name>
<email>phil.edworthy@renesas.com</email>
</author>
<published>2019-03-19T15:52:05+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=57a9f6e7eefa697349ff4823f178fd56abe27345'/>
<id>urn:sha1:57a9f6e7eefa697349ff4823f178fd56abe27345</id>
<content type='text'>
The Synopsys SSI driver uses a mandatory clock that is not documented,
so detail it in the device tree bindings. Also correct the spelling of
"pins" in the "Optional Properties" section for the driver.

Signed-off-by: Phil Edworthy &lt;phil.edworthy@renesas.com&gt;
Signed-off-by: Gareth Williams &lt;gareth.williams.jx@renesas.com&gt;
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
</content>
</entry>
<entry>
<title>spi: spi-fsl-spi: support use of the SPISEL_BOOT signal on MPC8309</title>
<updated>2019-03-18T14:47:24+00:00</updated>
<author>
<name>Rasmus Villemoes</name>
<email>rasmus.villemoes@prevas.dk</email>
</author>
<published>2019-03-06T10:32:05+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=69b921acae8a5b7feef03921d9b42c3634f3b9d1'/>
<id>urn:sha1:69b921acae8a5b7feef03921d9b42c3634f3b9d1</id>
<content type='text'>
The MPC8309 has a dedicated signal, SPISEL_BOOT, usually used as chip
select for the flash device from which the bootloader is loaded. It is
not an ordinary gpio, but is simply controlled via the SPI_CS register
in the system configuration.

To allow accessing such a spi slave, we need to teach
fsl_spi_cs_control() how to control the SPISEL_BOOT signal. To
distinguish the gpio-controlled slaves, continue to have those use
chip_select values of 0..ngpios-1, and use chip_select == ngpios for
the boot flash.

I'm not too happy with all the ifdeffery, but it seems to be necessary
for guarding the sysdev/fsl_soc.h and use of
get_immrbase() (spi-fsl-lib.c already contains similar ifdeffery).

Googling suggests that the MPC8306 is similar, with the SPI_CS
register at the same offset.

Signed-off-by: Rasmus Villemoes &lt;rasmus.villemoes@prevas.dk&gt;
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
</content>
</entry>
<entry>
<title>doc: lpspi: Document DT bindings for LPSPI clocks</title>
<updated>2019-03-18T12:16:51+00:00</updated>
<author>
<name>Clark Wang</name>
<email>xiaoning.wang@nxp.com</email>
</author>
<published>2019-03-06T06:30:36+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=addb32866d99068307f8eddb282ebb325d18446f'/>
<id>urn:sha1:addb32866d99068307f8eddb282ebb325d18446f</id>
<content type='text'>
Add introductions of clocks and clock-names strings.

Signed-off-by: Clark Wang &lt;xiaoning.wang@nxp.com&gt;
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
</content>
</entry>
<entry>
<title>spi: sifive: Add DT documentation for SiFive SPI controller</title>
<updated>2019-02-19T15:28:43+00:00</updated>
<author>
<name>Yash Shah</name>
<email>yash.shah@sifive.com</email>
</author>
<published>2019-02-19T11:40:06+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=3b155e873a38c3b28e419da759cfe86c74b1c870'/>
<id>urn:sha1:3b155e873a38c3b28e419da759cfe86c74b1c870</id>
<content type='text'>
DT documentation for SPI controller added.

Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
Signed-off-by: Emil Renner Berthing &lt;kernel@esmil.dk&gt;
Signed-off-by: Yash Shah &lt;yash.shah@sifive.com&gt;
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
</content>
</entry>
</feed>
