Intel OpenBMC Linux kernel source tree (mirror) https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev-5.4 2020-07-22T07:32:52+00:00 2020-07-22T07:32:52+00:00 Kangmin Park l4stpr0gr4m@gmail.com 2020-06-25T13:51:58+00:00 urn:sha1:43046f786714f75aa833c7c8e4ae649099979d94 [ Upstream commit 35b9c0fdb9f666628ecda02b1fc44306933a2d97 ] Fix unit address to match the first address specified in the reg property of the node in example. Signed-off-by: Kangmin Park <l4stpr0gr4m@gmail.com> Link: https://lore.kernel.org/r/20200625135158.5861-1-l4stpr0gr4m@gmail.com Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org> 2019-09-19T21:01:47+00:00 Linus Torvalds torvalds@linux-foundation.org 2019-09-19T21:01:47+00:00 urn:sha1:b682242f6012dddf81ef94b7ce5d2ec5ac8f8047 Pull mailbox updates from Jassi Brar: - qcom: - enable support for ipq8074, sm1850 and sm7180 - add child device node for qcs404 - misc fixes - mediatek: - enable support for mt8183 - misc rejig of cmdq driver - new client-reg dt property - armada: - use device-managed registration api * tag 'mailbox-v5.4' of git://git.linaro.org/landing-teams/working/fujitsu/integration: mailbox: qcom-apcs: fix max_register value mailbox: qcom: Add support for IPQ8074 APCS dt-bindings: mailbox: qom: Add ipq8074 APPS compatible mailbox: qcom: Add support for Qualcomm SM8150 and SC7180 SoCs dt-bindings: mailbox: Add APSS shared for SM8150 and SC7180 SoCs mbox: qcom: replace integer with valid macro mbox: qcom: add APCS child device for QCS404 mailbox: mediatek: cmdq: clear the event in cmdq initial flow mailbox: mediatek: cmdq: support mt8183 gce function mailbox: mediatek: cmdq: move the CMDQ_IRQ_MASK into cmdq driver data dt-binding: gce: add binding for gce client reg property dt-binding: gce: add gce header file for mt8183 dt-binding: gce: remove thread-num property mailbox: armada-37xx-rwtm: Use device-managed registration API 2019-09-17T05:51:05+00:00 Gokul Sriram Palanisamy gokulsri@codeaurora.org 2019-09-13T11:56:07+00:00 urn:sha1:7090a4716972224912151d73dca4b84c09486a8a Add mailbox support required in IPQ8074 SoCs. Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org> 2019-09-17T05:46:18+00:00 Sibi Sankar sibis@codeaurora.org 2019-08-07T07:09:54+00:00 urn:sha1:c0f5366f1472577f2db1d35d65a36646360d59b3 Add SM8150 and SC7180 APSS shared to the list of possible bindings. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org> 2019-09-17T05:40:05+00:00 Bibby Hsieh bibby.hsieh@mediatek.com 2019-08-29T01:48:09+00:00 urn:sha1:2d645217f1982190a54b2b0cb5f5ca42ec4d165e cmdq driver provide a function that get the relationship of sub system number from device node for client. add specification for #subsys-cells, mediatek,gce-client-reg. Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org> 2019-09-17T05:40:05+00:00 Bibby Hsieh bibby.hsieh@mediatek.com 2019-08-29T01:48:08+00:00 urn:sha1:8fedf805fa42842c0ef0aece9dbee957d805a8ea Add documentation for the mt8183 gce. Add gce header file defined the gce hardware event, subsys number and constant for mt8183. Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org> 2019-09-17T05:40:05+00:00 Bibby Hsieh bibby.hsieh@mediatek.com 2019-08-29T01:48:07+00:00 urn:sha1:472dff037178dffdf28b8d942f1b32c1b2531ad8 "thread-num" is an unused property so we remove it from example. Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org> 2019-08-13T22:11:00+00:00 Neil Armstrong narmstrong@baylibre.com 2019-08-08T08:51:31+00:00 urn:sha1:8d63f97113a7e474b4fbbdc6ccde1091da167211 Now that we have the DT validation in place, let's convert the device tree bindings for the Amlogic MHU controller over to a YAML schemas. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Rob Herring <robh@kernel.org> 2019-07-11T04:08:43+00:00 Suman Anna s-anna@ti.com 2019-06-04T17:01:45+00:00 urn:sha1:8c665292ec1263c627df60d10619e6f96deea788 The TI K3 AM65x and J721E family of SoCs have a new Mailbox IP that is based on the existing Mailbox IP present in OMAP architecture based SoCs. Update the existing OMAP Mailbox bindings for this new IP present on TI K3 AM65x and J721E SoCs. The same compatible from AM65x SoCs is reused for J721E SoCs. Signed-off-by: Suman Anna <s-anna@ti.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org> 2019-05-09T05:41:00+00:00 Marek Behun marek.behun@nic.cz 2019-03-31T03:15:32+00:00 urn:sha1:004c35cd8e0c81e0b4a34f0ad3ab0c4937ccaaea This adds device tree binding documentation for the rWTM BIU mailbox driver on the Armada 37xx SOC (EspressoBin, Turris Mox). Signed-off-by: Marek Behun <marek.behun@nic.cz> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>