BMC/Intel-BMC/linux.git, branch dev-5.2

ARM: configs: aspeed-g5: Enable ext4 and dm

2019-09-10T23:18:23+00:00

Signed-off-by: Joel Stanley

ARM: dts: aspeed-g6: Add gpio devices

2019-09-10T17:29:57+00:00

The AST2600 has 208 normal GPIO pins and 36 1.8V GPIOs. OpenBMC-Staging-Count: 1 Signed-off-by: Rashmica Gupta Signed-off-by: Joel Stanley

gpio: Add in ast2600 details to Aspeed driver

2019-09-10T17:29:57+00:00

The ast2600 is a new generation of SoC from ASPEED. Similarly to the ast2400 and ast2500, it has a GPIO controller for it's 3.3V GPIO pins. Additionally, it has a GPIO controller for 1.8V GPIO pins. As the register names for both controllers are the same and the 36 1.8V GPIOs and the first 36 of the 3.3V GPIOs are all bidirectional, we can use the same configuration struct and use the ngpio property to differentiate between the two sets of GPIOs. OpenBMC-Staging-Count: 1 Signed-off-by: Rashmica Gupta Signed-off-by: Joel Stanley

gpio/aspeed: Use ngpio property from device tree if available

2019-09-10T17:29:57+00:00

Use the ngpio property from the device tree if it exists. If it doesn't then fallback to the hardcoded value in the config. This is in preparation for adding ast2600 support. The ast2600 SoC has two GPIO controllers and so requires two instances of the GPIO driver. We use the ngpio property to different between them as they have different numbers of GPIOs. OpenBMC-Staging-Count: 1 Signed-off-by: Rashmica Gupta Reviewed-by: Joel Stanley Signed-off-by: Joel Stanley

gpio/aspeed: Setup irqchip dynamically

2019-09-10T17:29:57+00:00

This is in preparation for adding ast2600 support. The ast2600 SoC requires two instances of the GPIO driver as it has two GPIO controllers. Each instance needs it's own irqchip. OpenBMC-Staging-Count: 1 Signed-off-by: Rashmica Gupta Reviewed-by: Joel Stanley Signed-off-by: Joel Stanley

dt-bindings: gpio: aspeed: Update documentation with ast2600 controllers

2019-09-10T17:29:57+00:00

The ast2600 is a new generation of SoC from ASPEED. Similarly to the ast2400 and ast2500, it has a GPIO controller for it's 3.3V GPIO pins. Additionally, it has a GPIO controller for 36 1.8V GPIO pins. We use the ngpio property to differentiate between these controllers. OpenBMC-Staging-Count: 1 Signed-off-by: Rashmica Gupta Signed-off-by: Joel Stanley

gpio/aspeed: Fix incorrect number of banks

2019-09-10T17:29:57+00:00

The current calculation for the number of GPIO banks is only correct if the number of GPIOs is a multiple of 32 (if there were 31 GPIOs we would currently say there are 0 banks, which is incorrect). OpenBMC-Staging-Count: 1 Fixes: 361b79119a4b7 ('gpio: Add Aspeed driver') Signed-off-by: Rashmica Gupta Reviewed-by: Andrew Jeffery Reviewed-by: Joel Stanley Signed-off-by: Joel Stanley

gpio: aspeed: Pass irqchip when adding gpiochip

2019-09-10T17:29:49+00:00

We need to convert all old gpio irqchips to pass the irqchip setup along when adding the gpio_chip. For more info see drivers/gpio/TODO. For chained irqchips this is a pretty straight-forward conversion. Cc: Joel Stanley Cc: Andrew Jeffery Cc: Benjamin Herrenschmidt Cc: Thierry Reding Link: https://lore.kernel.org/r/20190809125515.19094-1-linus.walleij@linaro.org Reviewed-by: Andrew Jeffery Tested-by: Andrew Jeffery Acked-by: Joel Stanley Signed-off-by: Linus Walleij (cherry picked from commit 8512ee31926296fd7d65c1b3c97bb20d67e7eb2a) Signed-off-by: Joel Stanley

Merge tag 'v5.2.14' into dev-5.2

2019-09-10T13:43:25+00:00

This is the 5.2.14 stable release Signed-off-by: Joel Stanley

Linux 5.2.14

2019-09-10T09:35:27+00:00