BMC/Intel-BMC/linux.git, branch dev-5.10.46-intel

Merge branch 'dev-5.10' into dev-5.10-intel

2021-07-01T18:50:09+00:00

This is the 5.10.46 stable release. Signed-off-by: Jae Hyun Yoo

fixup! i2c: Add mux hold/unhold msg types

2021-06-28T17:37:30+00:00

It replaces timer callback with delayed work to avoid deadlock. Tested: Passed over weekend stress test. Signed-off-by: Jae Hyun Yoo Change-Id: I123cacabe7c1a5988f6356deeee03a6996b87141

ARM: dts: everest: Add phase corrections for eMMC

2021-06-28T04:04:02+00:00

The values were determined experimentally via boot tests, not by measuring the bus behaviour with a scope. We plan to do scope measurements to confirm or refine the values and will update the devicetree if necessary once these have been obtained. However, with the patch we can write and read data without issue, where as booting the system without the patch failed at the point of mounting the rootfs. OpenBMC-Staging-Count: 1 Signed-off-by: Andrew Jeffery Link: https://lore.kernel.org/r/20210628013605.1257346-1-andrew@aj.id.au Signed-off-by: Joel Stanley

ARM: dts: tacoma: Add phase corrections for eMMC

2021-06-28T04:03:59+00:00

The degree values were reversed out from the magic tap values of 7 (in) and 15 + inversion (out) initially suggested by Aspeed. With the patch tacoma survives several gigabytes of reads and writes using dd while without it locks up randomly during the boot process. OpenBMC-Staging-Count: 1 Signed-off-by: Andrew Jeffery Link: https://lore.kernel.org/r/20210625061017.1149942-1-andrew@aj.id.au Signed-off-by: Joel Stanley

Merge tag 'v5.10.46' into dev-5.10

2021-06-24T12:13:11+00:00

This is the 5.10.46 stable release Signed-off-by: Joel Stanley

ARM: dts: aspeed: p10bmc: Enable KCS channel 2

2021-06-24T09:24:01+00:00

Rainier uses KCS channel 2 as the source for the debug-trigger application outlined at [1] and implemented at [2]. [1] https://github.com/openbmc/docs/blob/master/designs/bmc-service-failure-debug-and-recovery.md [2] https://github.com/openbmc/debug-trigger OpenBMC-Staging-Count: 1 Signed-off-by: Andrew Jeffery Link: https://lore.kernel.org/r/20210623033854.587464-8-andrew@aj.id.au Signed-off-by: Joel Stanley

ARM: dts: aspeed: p10bmc: Switch to KCS 3 for MCTP binding

2021-06-24T09:23:50+00:00

The reset state of the status bits on KCS 4 is inappropriate for the MCTP LPC binding. Switch to KCS 3 which has a different reset behaviour. OpenBMC-Staging-Count: 1 Signed-off-by: Andrew Jeffery Link: https://lore.kernel.org/r/20210623033854.587464-7-andrew@aj.id.au Signed-off-by: Joel Stanley

misc: Remove obsolete mctp-lpc chardev

2021-06-24T09:23:28+00:00

The mctp-lpc chardev is replaced (temporarily) by the raw KCS chardev. The raw chardev is required for IBM's purposes until Jeremy's socket-based MCTP patches are merged[1][2]. [1] https://github.com/openbmc/docs/blob/master/designs/mctp/mctp-kernel.md [2] https://lore.kernel.org/openbmc/f4f5fa66542401e8d5e78c1fb30153195d384b62.camel@codeconstruct.com.au/ OpenBMC-Staging-Count: 1 Signed-off-by: Andrew Jeffery Link: https://lore.kernel.org/r/20210623033854.587464-6-andrew@aj.id.au Signed-off-by: Joel Stanley

ARM: dts: p10bmc: Drop the openbmc, mctp-lpc node

2021-06-24T09:23:24+00:00

The MCTP LPC driver was loaded by hacking up the compatible in the devicetree node for KCS 4. With the introduction of the raw KCS driver this hack is no-longer required. Use the regular compatible string for KCS 4 and configure the appropriate SerIRQ. OpenBMC-Staging-Count: 1 Signed-off-by: Andrew Jeffery Link: https://lore.kernel.org/r/20210623033854.587464-5-andrew@aj.id.au Signed-off-by: Joel Stanley

ARM: configs: Enable IPMI KCS raw chardev

2021-06-24T09:23:19+00:00

The raw KCS chardev is used by libmctp's vendor-defined LPC binding. OpenBMC-Staging-Count: 1 Signed-off-by: Andrew Jeffery Link: https://lore.kernel.org/r/20210623033854.587464-4-andrew@aj.id.au Signed-off-by: Joel Stanley