BMC/Intel-BMC/linux.git, branch dev-4.7

drivers: occ: Fix read length

2017-05-24T21:03:26+00:00

missing a line from patch manipulation. Signed-off-by: Edward A. James Signed-off-by: Patrick Williams

drivers: fsi: Fix SBE/OCC for 2 socket properly.

2017-05-24T05:06:26+00:00

Also update dts. Signed-off-by: Edward A. James Signed-off-by: Patrick Williams Reviewed-by: Christopher Bostic

ARM: dts: aspeed: witherspoon: Add example sbefifo and occfifo devices

2017-05-02T15:06:58+00:00

A possible implementation of the bindings for SBEFIFO device and OCC "FIFO" device. Use a phandle to reference the appropriate SBE device from the OCC entry. Signed-off-by: Edward A. James Signed-off-by: Patrick Williams

drivers: fsi: sbefifo: Add OCC driver

2017-05-02T15:06:50+00:00

Add a driver to control communications with the OCC on the POWER9. The driver communicates with OCC SRAM using the FSI SBEFIFO driver. The format of the communication is a command followed by response. The sequence must be done atomically. The driver performs these operations asynchronously, such that a write operation starts the command, and a read will gather the response data. Signed-off-by: Edward A. James Signed-off-by: Patrick Williams

drivers: fsi: sbefifo: Add in-kernel API

2017-05-02T15:06:34+00:00

Add exported functions to the SBEFIFO driver to open/write/read/close from within the kernel. Signed-off-by: Edward A. James Signed-off-by: Patrick Williams

ARM: aspeed: witherspoon: Take UART1 out of reset

2017-05-01T18:53:51+00:00

This is required so the UART can be used before booting the host. Signed-off-by: Joel Stanley Reviewed-by: Andrew Jeffery Signed-off-by: Patrick Williams

drivers/fsi: Add FSI SBEFIFO driver

2017-05-01T18:53:46+00:00

IBM POWER9 processors contain some embedded hardware and software bits collectively referred to as the self boot engine (SBE). One role of the SBE is to act as a proxy that provides access to the registers of the POWER chip from other (embedded) systems. The POWER9 chip contains a hardware frontend for communicating with the SBE from remote systems called the SBEFIFO. The SBEFIFO logic is contained within an FSI CFAM (see Documentation/fsi) and as such the driver implements an FSI bus device. The SBE expects to communicate using a defined wire protocol; however, the driver knows nothing of the protocol and only provides raw access to the fifo device to userspace applications wishing to communicate with the SBE using the wire protocol. The SBEFIFO consists of two hardware fifos. The upstream fifo is used by the driver to transfer data to the SBE on the POWER chip, from the system hosting the driver. The downstream fifo is used by the driver to transfer data from the SBE on the power chip to the system hosting the driver. Signed-off-by: Brad Bishop Reviewed-by: Eddie James Signed-off-by: Patrick Williams

drivers: fsi: Fix hub unregistration

2017-05-01T18:53:43+00:00

Hub master unregistration was missing a few things. Signed-off-by: Edward A. James Signed-off-by: Patrick Williams

drivers/fsi: Set IRQ masks along hub path

2017-05-01T18:53:40+00:00

Enable/disable client engine IRQ masks including those along the hub path to a particular engine. This includes slave MMODE i-poll, Si1M, SRSIM, and hub master MSIEP. Signed-off-by: Christopher Bostic Signed-off-by: Edward A. James Signed-off-by: Patrick Williams

drivers/fsi: Scan for hub link IRQ sources

2017-05-01T18:53:37+00:00

Look for the hub link that may have sourced the IRQ being handled. Clear out hub link interrupting conditions that are latched in hardware after FSI client handler has been dispatched. Signed-off-by: Christopher Bostic Signed-off-by: Edward A. James Signed-off-by: Patrick Williams